A new generation 16-bit general purpose programmable DSP and its video rate application

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Abstract
A new generation 16-bit fixed point general purpose DSP (m/spl mu/ PD77016) is developed. A register architecture with 8-general purpose registers is newly introduced to the 16-bit DSP to achieve high performance with low cost. Having enough general purpose registers, fast algorithms which require unregular computation such as fast DCT can be efficiently implemented without overheads of many register load/stores. This reduces the number of instruction cycles to implement these algorithms by the DSP compared with the DSPs having fewer registers. Reductions in the number of instruction cycles in realizing applications enable both reductions in the number of chips or in clock frequency which result in lowering power consumptions. By using fast DCT algorithm suitable for the DSP architecture, an 8-point DCT including I/O operations is realized in 35 instruction cycles which is less than the half of the instruction cycles required for the original algorithm based on a matrix vector multiplication. DCT (IDCT) part of MPEG encoding/decoding for typical sequence (352 pels /spl times/ 240 lines, 30 frames/sec) is realized by one 33 MHz /spl mu/PD77016 (30ns instruction cycle).

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