High-performance subquarter-micrometer gate CMOS technology
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 11 (4) , 134-136
- https://doi.org/10.1109/55.61787
Abstract
A single phosphorous-doped poly(n/sup +/)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22- mu m-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16- mu m gate length and pMOSFETs of 0.22- mu m gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V.<>Keywords
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