Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Several methods accelerating fault simulation for combinational circuits using parallel pattern evaluation are presented. All methods make use of a very efficient data structure which allows the easy recognition of special situations that can be used to avoid a lot of gate evaluations during explicit fault simulation. An implementation of the concepts shows that the resulting fault simulation algorithm is very fast. The proposals and the improved data structure considerably enhance the performance of the standard algorithmKeywords
This publication has 2 references indexed in Scilit:
- Structure based methods for parallel pattern fault simulation in combinational circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Accelerated Fault Simulation and Fault Grading in Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987