Low-voltage coefficient capacitors for VLSI processes

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Abstract
The addition of a high-quality capacitor structure to a 1- mu m digital CMOS process is considered to allow the fabrication of mixed analog and digital VLSI circuits. Two approaches have been examined which require minimal changes in the existing process. The first involves a high-dose arsenic implant through the thin (225 A) gate oxide to produce n/sup +/ single-crystal silicon bottom plates. This approach produced a capacity of 154 nF/cm/sup 2/ with a maximum voltage coefficient of 210 p.p.m./V over a bias range of +or-7.5 V. In the second approach the high-dose implant is performed prior to the gate oxidation. Impurity-concentration-enhanced oxidation of the n/sup +/ silicon bottom plates can then be exploited during the subsequent gate oxidation to grow simultaneously a capacitor dielectric of varying thickness. Capacities of 40-90 nF/cm/sup 2/ have been produced with voltage coefficients ranging from 35 to 125 p.p.m./V, respectively.