Verification of timed circuits with symbolic delays
- 12 April 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented as symbols. The approach discovers a set of sufficient linear constraints on the symbols that guarantee the correctness of the circuit. Experimental results from the area of asynchronous circuits show the applicability of the approach. Author(s) Clariso, R. Universitat Politecnica de Catalunya Cortadella, J.Keywords
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