Modeling Latch-Up in CMOS Integrated Circuits
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 1 (4) , 157-162
- https://doi.org/10.1109/tcad.1982.1270006
Abstract
Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.Keywords
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