A 29 ns 64 Mb DRAM with hierarchical array architecture

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 246-247
https://doi.org/10.1109/isscc.1995.535541

Abstract

This paper describes the experimental results of a 64 Mb DRAM test chip fabricated in 0.25 /spl mu/m CMOS using a segment driver circuit in a hierarchical word line scheme for shrinkability to the next-generation high-speed high-density DRAM. This approach is applicable to the prior generation.

Keywords

RANDOM ACCESS MEMORY
DRIVER CIRCUITS
VOLTAGE
SWITCHES
TIMING
DELAY EFFECTS
WIRING
CIRCUIT TESTING
MOS DEVICES
CMOS MEMORY CIRCUITS

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IEEE Journal of Solid-State Circuits, 1991