Effects of a lightly-doped-drain (LDD) implantation condition on the device characteristics of polycrystalline-Si thin-film transistors

This publication has 7 references indexed in Scilit:

• Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment
  IEEE Electron Device Letters, 1999
• Numerical analysis of poly-TFTs under off conditions
  Solid-State Electronics, 1997
• Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's
  IEEE Transactions on Electron Devices, 1995
• Characteristics of offset-structure polycrystalline-silicon thin-film transistors
  IEEE Electron Device Letters, 1988
• Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's
  IEEE Electron Device Letters, 1987
• Anomalous leakage current in LPCVD PolySilicon MOSFET's
  IEEE Transactions on Electron Devices, 1985
• Structure-enhanced MOSFET degradation due to hot-electron injection
  IEEE Electron Device Letters, 1984