A detailed analysis of GOS defects in MOS transistors: testing implications at circuit level
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 544-551
- https://doi.org/10.1109/test.1995.529882
Abstract
The properties of Gate Oxide Short defects (GOS) in CMOS circuits are investigated identifying the most relevant parameters that determine the behavior of a defective device. Electrical models of the defect are developed and compared with experimentation. Depending upon location and transistor type, GOSs are resistive, diode, parasitic MOSFET or parasitic BJT. We also investigate the necessary conditions to detect a GOS at the circuit level, providing the bases for an efficient ATPG approach.Keywords
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