Reduced complexity symbol detectors with parallel structure for ISI channels

This publication has 20 references indexed in Scilit:

• Algorithms and architectures for concurrent Viterbi decoding
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A block processing method for designing high-speed Viterbi detectors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Breadth-first trellis decoding with adaptive effort
  IEEE Transactions on Communications, 1990
• Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck
  IEEE Transactions on Communications, 1989
• Locally connected VLSI architectures for the Viterbi algorithm
  IEEE Journal on Selected Areas in Communications, 1988
• Reduced-state sequence estimation with set partitioning and decision feedback
  IEEE Transactions on Communications, 1988
• Correlative level coding and maximum-likelihood decoding
  IEEE Transactions on Information Theory, 1971
• Optimal receiver design for convolutional codes and channels with memory via control theoretical concepts
  Information Sciences, 1971
• On optimum receivers for channels having memory (Corresp.)
  IEEE Transactions on Information Theory, 1968
• Error bounds for convolutional codes and an asymptotically optimum decoding algorithm
  IEEE Transactions on Information Theory, 1967