Methods for Calculating SEU Rates for Bipolar and NMOS Circuits

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Abstract
Computer codes developed at Clarkson for simulating charge generation by proton-induced nuclear reactions in well-defined silicon microstructures can be used to calculate SEU rates for specific devices when the critical charge and the dimensions of all SEU sensitive junctions on the device are known, provided one can estimate the contribution from externally-generated charge which enters the sensitive junction by drift and diffusion. Calculations for two important bipolar devices, the AMD 2901B bit slice and the Fairchild 93L422 RAM, for which the dimensions of the sensitive volumes were estimated from available heavy-ion test data, have been found to be in agreement with experimental data. Circuit data for the Intel 2164A, an alpha sensitive dRAM, was provided by the manufacturer. Calculations based on crude assumptions regarding which nuclear recoils and which alphas trigger upsets in the 2164A were found to agree with experimental data.