A 0.5 V/100 MHz over-V/sub CC/ grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

This publication has 3 references indexed in Scilit:

• A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002