FPGA placement by using Hopfield neural network

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Abstract
Purpose – The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement. Design/methodology/approach – Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run-time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented. Findings – The Hopfield network and parallel placement give comparable placements with the method using a simulated annealing algorithm. The parallel placement enables a decrease in total number of neurons and neuron connections which are necessary for simultaneous placement of all cells in a circuit. Research limitations/implications – This work provides a starting-point for further research under hardware realization of the cell placement by using the Hopfield network. The presented solutions can be used for FPGA, gate array, sea-of-gates circuits and standard cell circuits with the same size cells. Originality/value – The Hopfield network is used for placement in real circuits, in which nets contain multiple terminals, and for processing units in a parallel placement.
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