Electroless Copper Deposition on Metals and Metal Silicides

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Abstract
Chemical plating techniques have been used in silicon processing for many years for junction delineation and ohmic contact formation. In recent years, interest in this area has been renewed because of the potential use of electroless copper deposition for ultra-large-scale integration (ULSI) metallization and for the formation of thin metal etch masks for deep-ultraviolet lithography. Good deposition selectivity, low operating temperature, high copper purity, good filling characteristics, and planar topography have been among the many advantageous attributes reported from early investigations.In the June 1993 issue of theMRS Bulletinon Copper Metallization, Cho et al. gave an exposition on the use of electroless copper for VLSI. More comprehensive reviews of the electrochemical fundamentals can be found in References 8,9, and 10. This article summarizes the current understanding of various chemical and material aspects of this deposition method in an attempt to give an overview of the film growth characteristics for thin film applications. Because of length limitations, only selected topics are included. The emphasis is on the initiation conditions and the resultant microstructure and properties obtained. We also discuss special considerations for fine pattern formation.The information presented here applies primarily to electroless copper deposition on metals and metal silicides since these are the typical substrate surfaces for metallization in contact vias of ULSI circuits. Strictly speaking, metallization of upper-level interconnects occurs mostly on a dielectric base. However, since copper systems usually require a diffusion barrier to shield the copper from diffusing into the silicon, we can treat the deposition process startingfrom this layer onward.