Low-power and low-voltage CMOS digital design

This publication has 14 references indexed in Scilit:

• Cost, power, and parallelism in speech signal processing
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Low power design using double edge triggered flip-flops
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
• A state assignment approach to asynchronous CMOS circuit design
  IEEE Transactions on Computers, 1994
• Saving power by synthesizing gated clocks for sequential circuits
  IEEE Design & Test of Computers, 1994
• Circuit activity based logic synthesis for low power reliable operations
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
• A voltage reduction technique for battery-operated systems
  IEEE Journal of Solid-State Circuits, 1990
• High-speed CMOS circuit technique
  IEEE Journal of Solid-State Circuits, 1989
• CODYMOS frequency dividers achieve low power consumption and high frequency
  Electronics Letters, 1973
• Synthesis of Networks with a Minimum Number of Negative Gates
  IEEE Transactions on Computers, 1971
• Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements
  IEEE Transactions on Computers, 1968