Design and implementation of a totally self-checking 16 × 16 bit array multiplier
- 1 December 1992
- journal article
- Published by Elsevier in Integration
- Vol. 14 (2) , 215-228
- https://doi.org/10.1016/0167-9260(92)90027-v
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
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- An 0(n) Parallel Multiplier with Bit-Sequential Input and OutputIEEE Transactions on Computers, 1979