A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

30 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 486-612 Vol. 1
https://doi.org/10.1109/isscc.2005.1494081

Abstract

A 6-stage fully pipelined embedded SRAM is implemented in a 90nm SOI technology. The array uses a conventional 6-transistor memory cell and sense amplifier to achieve the cycle time while minimizing the impact of device variation. A sum-addressed pre-decoder allows partial activation for power savings.

Keywords

RANDOM ACCESS MEMORY
DECODING
STREAMING MEDIA
WIRE
PROCESS DESIGN
ACCELERATION
BUFFER STORAGE
READ-WRITE MEMORY
PIPELINES
REGISTERS

This publication has 2 references indexed in Scilit:

A streaming processing unit for a CELL processor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003