TELE: a timing evaluator using layout estimation for high level applications
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- Accurate prediction of physical design characteristics for random logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A new area and shape function estimation technique for VLSI layoutsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- LAST: a layout area and shape function estimator for high level applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A fast physical constraint generator for timing driven layoutPublished by Association for Computing Machinery (ACM) ,1991
- Average interconnection length and interconnection distribution based on rent's rulePublished by Association for Computing Machinery (ACM) ,1989
- On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A Linear-Time Heuristic for Improving Network PartitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Connectivity of Random LogicIEEE Transactions on Computers, 1982
- Placement and average interconnection lengths of computer logicIEEE Transactions on Circuits and Systems, 1979
- On a Pin Versus Block Relationship For Partitions of Logic GraphsIEEE Transactions on Computers, 1971