A High-Performance N-MOS Adder Designed for Optimized Cryogenic Operation
- 1 June 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (3) , 404-410
- https://doi.org/10.1109/jssc.1986.1052542
Abstract
No abstract availableKeywords
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