Energy consumption modeling and optimization for SRAM's

This publication has 24 references indexed in Scilit:

• Predicting and scaling power consumption in CMOS ASICs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Automatic transistor sizing in high performance CMOS logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A 3.3-V 12-ns 16-Mb CMOS SRAM
  IEEE Journal of Solid-State Circuits, 1992
• McPOWER: a Monte Carlo approach to power estimation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1992
• A 21-mW 4-Mb CMOS SRAM for battery operation
  IEEE Journal of Solid-State Circuits, 1991
• Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's
  IEEE Journal of Solid-State Circuits, 1991
• A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell
  IEEE Journal of Solid-State Circuits, 1990
• A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture
  IEEE Journal of Solid-State Circuits, 1990
• A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current
  IEEE Journal of Solid-State Circuits, 1990
• A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM
  IEEE Journal of Solid-State Circuits, 1983