A high speed 16 kbit ECL RAM
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5) , 509-514
- https://doi.org/10.1109/jssc.1983.1051985
Abstract
A 16384 /spl times/ 1 bit ECL RAM (emitter coupled logic random access memory) with an access time of 15 ns and a power dissipation of 700 mW has been developed. The high packing density and performance were achieved by using a p-n-p load cell, a novel ECL circuit, and U-groove isolation. The test results proved that a p-n-p load cell is very effective in producing a fast high-density bipolar RAM having a capacity of over 64 Kbits.Keywords
This publication has 4 references indexed in Scilit:
- A 100ns 256K DRAM with page-nibble modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A sub 100ns 256K DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A 3-ns 1-kbit RAM using super self-aligned process technologyIEEE Journal of Solid-State Circuits, 1981
- A fast 7.5 ns access 1K-bit RAM for cache-memory systemsIEEE Journal of Solid-State Circuits, 1978