A 3-ns 1-kbit RAM using super self-aligned process technology
- 1 October 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 16 (5) , 424-429
- https://doi.org/10.1109/jssc.1981.1051617
Abstract
A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.Keywords
This publication has 5 references indexed in Scilit:
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- A fast 7.5 ns access 1K-bit RAM for cache-memory systemsIEEE Journal of Solid-State Circuits, 1978
- A high performance 4K static RAM fabricated with an advanced MOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977