The role of an ultrathin silicon interlayer at the SiO2-Ge interface

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Abstract
Recent studies [Hattangady et al., Appl. Phys. Lett. 57, 581 (1990)] have shown greatly reduced interface state densities (5×1010 cm−2 eV−1) in Ge‐based, metal‐insulator‐semiconductor structures with the use of an ultrathin, pseudomorphic Si interlayer between the gate dielectric, SiO2, and the Ge semiconductor substrate. The Si and the SiO2 layers are deposited in situ and sequentially at low temperature (300 °C) in a remote‐plasma‐enhanced chemical‐vapor‐deposition system. This report presents an analysis of the Si‐Ge heterostructure before and after the SiO2 deposition. Low‐energy He ion scattering spectroscopy shows that the silicon layer (28 Å) provides complete coverage of the Ge surface prior to the deposition of the SiO2 film. The existence of the silicon interlayer after the remote‐plasma‐enhanced deposition of 150 Å of the SiO2 film is established by x‐ray photoelectron spectroscopy (XPS). Throughout a cumulative series of thin (∼10 Å) oxide depositions, XPS showed no evidence of Ge oxidation states other than Ge0+ (elemental Ge) at the interface. Quantitative XPS has been used to evaluate the extent of subcutaneous oxidation which could determine the amount of Si remaining at the interface and thereby influence the electrical properties of the semiconductor‐oxide interface. For the conditions studied, it is observed that oxidation consumes only 4 Å of the initial 28 Å of silicon. Furthermore, this is apparently due to the plasma oxidation of the silicon at the initiation of the remote oxygen plasma discharge. Subcutaneous oxidation is limited thereafter by the oxide film that forms a barrier to oxygen diffusion. In addition, the XPS analysis reveals several important characteristics of SiO2‐Si interface formation with these plasma‐deposited SiO2 dielectric films. Inversion‐mode, p‐channel Ge field‐effect transistors fabricated with this composite SiO2‐Si gate dielectric structure show a maximum room‐temperature transconductance of 52 mS mm−1 at a gate length of 2 μm and a peak effective channel hole mobility of 430 cm2 V−1 s−1. These devices exhibit negligible charge‐induced threshold shifts.