A datapath generator for full-custom macros of iterative logic arrays
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- A cascadable 200 GOPS motion estimation chip for HDTV applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new mapping technique for automated design of highly efficient multiplexed FIR digital filtersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Solid state [Development forecast]IEEE Spectrum, 1997
- Echelon: a multilayer detailed area routerIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- Design techniques for silicon compiler implementations of high-speed FIR digital filtersIEEE Journal of Solid-State Circuits, 1996
- Design of an ASIC for fast signal recognition and code acquisition in DS-SS-CDMA receiversPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1996
- Solid state [Trends/developments]IEEE Spectrum, 1996
- LILA: layout generation for iterative logic arraysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- Design of digital filters for advanced telecommunications ASIC's using a special-purpose silicon compilerIEEE Journal of Solid-State Circuits, 1991
- Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuitsIEEE Journal of Solid-State Circuits, 1984