Design techniques for silicon compiler implementations of high-speed FIR digital filters
- 1 May 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (5) , 656-667
- https://doi.org/10.1109/4.509848
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- An efficient 175 MHz programmable FIR digital filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- GENRIF: An integrated VLSI FIR filter compilerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Area-efficient VLSI implementation of FIR digital filters using shifted partial productsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automatic layout synthesis for FIR filters using a silicon compilerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A programmable 32 tap digital interpolation filter in 1.5 mu m CMOS with 80 MHz output data ratePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Vlsi programmable digital filter for video signal processingJournal of Signal Processing Systems, 1993
- An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficientsIEEE Transactions on Circuits and Systems, 1989
- The architectures and design of a 20-MHz real-time DSP chip setIEEE Journal of Solid-State Circuits, 1989
- FIR digital filters for high sample rate applicationsIEEE Communications Magazine, 1987
- Ultimate-Speed AddersIEEE Transactions on Electronic Computers, 1963