An efficient 175 MHz programmable FIR digital filter
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 72-75 vol.1
- https://doi.org/10.1109/iscas.1993.393660
Abstract
An efficient 175-MHz programmable finite impulse response (FIR) digital filter is implemented. It uses a novel switchable unit-delay to allocate the optimal hardware resources to each filter tap. The authors' prototype circuit can have up to 32 linear taps with 16-bit I/O in a die size of 5.9mm by 3.4mm using 1.2 /spl mu/m CMOS technology. A simple recoding of the coefficient values results in a simplification of the digit multiplication hardware. On-chip testing circuitry permits the testing of the chip at a high frequency.Keywords
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