SEU hardening of field programmable gate arrays (FPGAs) for space applications and device characterization
- 1 December 1994
- journal article
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 41 (6) , 2179-2186
- https://doi.org/10.1109/23.340560
Abstract
Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.Keywords
This publication has 3 references indexed in Scilit:
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