A reliable 1-Mbit DRAM with a multi-bit-test mode
- 1 October 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (5) , 909-913
- https://doi.org/10.1109/jssc.1985.1052414
Abstract
A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.Keywords
This publication has 6 references indexed in Scilit:
- A 90ns 1Mb DRAM with multi-bit test modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- An experimental 1Mb DRAM with on-chip voltage limiterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A highly reliable N-MOS process for one megabit dynamic random access memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 256K dynamic RAM with page-nibble modeIEEE Journal of Solid-State Circuits, 1983
- A 100 ns 5 V only 64Kx1 MOS dynamic RAMIEEE Journal of Solid-State Circuits, 1980
- A high performance sense amplifier for a 5 V dynamic RAMIEEE Journal of Solid-State Circuits, 1980