Suppressed threshold voltage roll-off characteristicof 40 nmgate length ultrathin SOI MOSFET
- 15 October 1998
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 34 (21) , 2069-2070
- https://doi.org/10.1049/el:19981433
Abstract
The authors have experimentally demonstrated a highly suppressed threshold voltage roll-off characteristic of a 40 nm gate length ultrathin (11 nm) silicon-on-insulator (SOI) n-MOSFET. It is observed that ΔVth is only 0.2 V when compared with a long gate length (150 nm) device. The marked effectiveness of an ultrathin SOI channel is experimentally confirmed to suppress the short-channel effect.Keywords
This publication has 6 references indexed in Scilit:
- Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 7.9/5.5 psec room/low temperature SOI CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 50-nm channel nMOSFET/SIMOX with an ultrathin 2- or 6-nm thick silicon layer and their significant features of operationsIEEE Electron Device Letters, 1997
- Epitaxial layer transfer by bond and etch back of porous SiApplied Physics Letters, 1994
- Scaling the Si MOSFET: from bulk to SOI to bulkIEEE Transactions on Electron Devices, 1992
- Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?Published by Institute of Electrical and Electronics Engineers (IEEE) ,1992