Gate sizing: a general purpose optimization approach

This publication has 14 references indexed in Scilit:

• Advanced library characterization for high-performance ASIC
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Gate sizing in MOS digital circuits with linear programming
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
  Published by Association for Computing Machinery (ACM) ,1995
• A survey of power estimation techniques in VLSI circuits
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
• Delay analysis of series-connected MOSFET circuits
  IEEE Journal of Solid-State Circuits, 1991
• Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
• Transistor size optimization in the tailor layout system
  Published by Association for Computing Machinery (ACM) ,1989
• Transistor sizing in CMOS circuits
  Published by Association for Computing Machinery (ACM) ,1987
• Aesop: a tool for automated transistor sizing
  Published by Association for Computing Machinery (ACM) ,1987
• An algorithm for CMOS timing and area optimization
  IEEE Journal of Solid-State Circuits, 1984