A dual granularity and globally interconnected architecture for a programmable logic device
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Optimization of field-programmable gate array logic block architecture for speedPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Flexibility of interconnection structures for field-programmable gate arraysIEEE Journal of Solid-State Circuits, 1991
- The effect of logic block complexity on area of programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989