Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines

Publisher Website

1 March 1979

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-28 (3) , 276-281
https://doi.org/10.1109/TC.1979.1675338

Abstract

This correspondence deals with a unification and extension of some previous work on self-checking (SC) and fail-safe (FS) systems.

Keywords

This publication has 10 references indexed in Scilit:

Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
IEEE Transactions on Computers, 1979
Design of Reliable Synchronous Sequential Circuits
IEEE Transactions on Computers, 1975
On-Line Diagnosis of Unrestricted Faults
IEEE Transactions on Computers, 1975
Note on Self-Checking Checkers
IEEE Transactions on Computers, 1974
Partially Self-Checking Circuits and Their Use in Performing Logical Operations
IEEE Transactions on Computers, 1974
On-Set Realization of Fail-Safe Sequential Machines
IEEE Transactions on Computers, 1974
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers, 1973
N-Fail-Safe Sequential Machines
IEEE Transactions on Computers, 1972
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
IEEE Transactions on Computers, 1971
Basic Properties and a Construction Method for Fail-Safe Logical Systems
IEEE Transactions on Electronic Computers, 1967