Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

This publication has 9 references indexed in Scilit:

• Introducing redundancy in field programmable gate arrays
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Node-covering based defect and fault tolerance methods for increased yield in FPGAs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Re-engineering of timing constrained placements for regular architectures
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• REMOD: a new methodology for designing fault-tolerant arithmetic circuits
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
• Challenges in CAD for the one million gate FPGA
  Published by Association for Computing Machinery (ACM) ,1997
• Architectural and physical design challenges for one-million gate FPGAs and beyond
  Published by Association for Computing Machinery (ACM) ,1997
• The yield enhancement of field-programmable gate arrays
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994
• Field-Programmable Gate Arrays
  Published by Springer Nature ,1992
• Tight bounds for minimax grid matching, with applications to the average case analysis of algorithms
  Published by Association for Computing Machinery (ACM) ,1986