On a Ternary Model of Gate Networks
- 1 March 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-28 (3) , 178-184
- https://doi.org/10.1109/tc.1979.1675317
Abstract
In this paper we formalize a ternary model which is being used to study the behavior of binary sequential gate networks. We first describe a binary model which is capable of a detailed description of network behavior, but involves a number of steps that grows exponentially in the number of gates. The complexity of the ternary model is linear in the number of gates;however, only partial information is obtained in generaL A mathematical theory is developed making precise these two models and the comparison between them. A number of examples illustrate these results. This work generalizes previously reported research.Keywords
This publication has 6 references indexed in Scilit:
- Ternary Simulation of Binary Gate NetworksPublished by Springer Nature ,1977
- Anomalous Behavior of Synchronizer and Arbiter CircuitsIEEE Transactions on Computers, 1973
- A Note on Three-Valued Logic SimulationIEEE Transactions on Computers, 1972
- A Heuristic Algorithm for the Testing of Asynchronous CircuitsIEEE Transactions on Computers, 1971
- A three-value computer design verification systemIBM Systems Journal, 1969
- Hazard Detection in Combinational and Sequential Switching CircuitsIBM Journal of Research and Development, 1965