A zero-overhead self-timed 160-ns 54-b CMOS divider
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11) , 1651-1661
- https://doi.org/10.1109/4.98986
Abstract
No abstract availableThis publication has 15 references indexed in Scilit:
- An NMOS 64b floating-point chip setPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Algorithm for high speed shared radix 8 division and radix 8 square rootPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stagesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A Zero-overhead Self-timed 160ns 54b CMOS DividerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- SPIM: a pipelined 64*64-bit iterative multiplierIEEE Journal of Solid-State Circuits, 1989
- Automatic synthesis of asynchronous circuits from high-level specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- IRSIM: an incremental MOS switch-level simulatorPublished by Association for Computing Machinery (ACM) ,1989
- The MIPS R3010 floating-point coprocessorIEEE Micro, 1988
- Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIBPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985