A 0.14mW/Gbps high-density capacitive interface for 3D system integration
- 1 January 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8/spl times/8/spl mu/m/sup 2/ enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.Keywords
This publication has 3 references indexed in Scilit:
- A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control schemePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Proximity communicationIEEE Journal of Solid-State Circuits, 2004
- 4 Gbps high-density AC coupled interconnectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003