A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme
- 30 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A 160Gb/s interface design configuration for multichip LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Ultra-thin chip with permalloy film for high performance MS/RF CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004