Analysis and reduction of glitches in synchronous networks
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 398-403
- https://doi.org/10.1109/edtc.1995.470365
Abstract
The influence of transition activity on dynamic power dissipation is analysed by examining three components: dissipation in combinational logic, flipflops and clock line. Transition activity is analysed by making a distinction between useful transitions and glitches (useless transitions). A transition counting and parity evaluation method is used for this. Most glitches can be eliminated by introducing flipflops using retiming and pipelining and/or by choosing different architectures. In this way an optimal level for pipelining can be found.Keywords
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