Cache performance of the SPEC92 benchmark suite
Open Access
- 1 August 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 13 (4) , 17-27
- https://doi.org/10.1109/40.229711
Abstract
The authors consider whether SPECmarks, the figures of merit obtained from running the SPEC benchmarks under certain specified conditions, accurately indicate the performance to be expected from real, live work loads. Miss ratios for the entire set of SPEC92 benchmarks are measured. It is found that instruction cache miss ratios in general, and data cache miss ratios for the integer benchmarks, are quite low. Data cache miss ratios for the floating-point benchmarks are more in line with published measurements for real work loads.Keywords
This publication has 16 references indexed in Scilit:
- Measuring VAX 8800 performance with a histogram hardware monitorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarksPublished by Association for Computing Machinery (ACM) ,1991
- The interaction of architecture and operating system designPublished by Association for Computing Machinery (ACM) ,1991
- Cache performance of the integer SPEC benchmarks on a RISCACM SIGARCH Computer Architecture News, 1990
- Evaluating associativity in CPU cachesIEEE Transactions on Computers, 1989
- Cache performance of operating system and multiprogramming workloadsACM Transactions on Computer Systems, 1988
- Accurate Unix benchmarking: art, science, or black magic?IEEE Micro, 1988
- Aspects of Cache Memory and Instruction Buffer PerformancePublished by Defense Technical Information Center (DTIC) ,1987
- Line (Block) Size Choice for CPU Cache MemoriesIEEE Transactions on Computers, 1987
- Cache MemoriesACM Computing Surveys, 1982