A family of user-programmable peripherals with a functional unit architecture
- 1 April 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (4) , 515-529
- https://doi.org/10.1109/4.126539
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- A 9000-gate user-programmable gate arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Flexibility of interconnection structures for field-programmable gate arraysIEEE Journal of Solid-State Circuits, 1991
- A user-programmable peripheral with functional unit architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Mappable memory subsystem for high speed applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 5000-gate CMOS EPLD with multiple logic and interconnect arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 50-ns 256 K CMOS split-gate EPROMIEEE Journal of Solid-State Circuits, 1988
- Novel circuit techniques for zero-power 25-ns CMOS erasable programmable logic devices (EPLDs)IEEE Journal of Solid-State Circuits, 1986