An 8K B random-access memory chip using the one-device FET cell
- 1 October 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (5) , 298-305
- https://doi.org/10.1109/jssc.1973.1050407
Abstract
Describes the design, fabrication, and testing of an 8192-b p-channel fully-functional random access memory. Novel features of this device are discussed. Among these are the following: inversion layer capacitor one-device cell; the use of a high speed buffer to maximize data transfer; and a minimization of cell pitch limitations through the use of a unique word system circuit design. Performance, power, and yields are also discussed.Keywords
This publication has 2 references indexed in Scilit:
- Subthreshold design considerations for insulated-gate field-effect transistorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Storage array and sense/refresh circuit for single-transistor memory cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1972