ESD Protection Reliability in 1μM CMOS Technologies

1 April 1986

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 199-205
https://doi.org/10.1109/irps.1986.362134

Abstract

The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.

Keywords

CMOS TECHNOLOGY
ELECTROSTATIC DISCHARGE
PROTECTION
CIRCUITS
DEGRADATION
FAILURE ANALYSIS
CONDUCTIVITY
SHEET MATERIALS
ELECTRONS
ISOLATION TECHNOLOGY

This publication has 3 references indexed in Scilit:

NMOS protection circuitry
IEEE Transactions on Electron Devices, 1985
Electro-Thermomigration in NMOS LSI Devices
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981
Second breakdown and damage in junction devices
IEEE Transactions on Electron Devices, 1973