Ultrathin high-K gate stacks for advanced CMOS devices
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 90, 20.1.1-20.1.4
- https://doi.org/10.1109/iedm.2001.979537
Abstract
Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.Keywords
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