Size Effect on Thermal Conduction in Silicon-on-Insulator Devices under Electrostatic Discharge (ESD) Conditions

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Abstract
Previous experimental work has shown degradation in the electrostatic discharge (ESD) failure voltage for silicon-on-insulator (SOI) devices compared to that of devices made from bulk silicon substrates. Understanding of this trend requires simulations of temperature fields in SOI devices using accurate thermal property values. The present work predicts the in-plane lattice thermal conductivity of thin silicon films at temperatures up to 1000 K considering the size effect due to phonon-boundary scattering. For silicon layers thinner than 0.2 µm, a significant reduction in the thermal conductivity is expected even at temperatures as high as 700 K. A compact expression for the thermal conductivity of thin silicon films can be readily used in device simulations. Temperature field predictions for a simplified SOI device show the impact of the size effect and motivate discussion of its implications for ESD buffer design.