Analog-binary CCD correlator: a VLSI signal processor
- 1 April 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (2) , 518-525
- https://doi.org/10.1109/jssc.1979.1051205
Abstract
Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code load logic, and TTL-to-MOS converters. Design of the floating-gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. Electron-beam lithography was used to produce photomasks with low defect density and tight dimensional tolerances over the array.Keywords
This publication has 6 references indexed in Scilit:
- Programmable CCD correlatorIEEE Transactions on Electron Devices, 1979
- IIB-1 noise measurements on buried-channel charge-coupled devicesIEEE Transactions on Electron Devices, 1975
- Surface potential equilibration method of setting charge in charge-coupled devicesIEEE Transactions on Electron Devices, 1975
- A 500-point fourier transform using charge-coupled devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1975
- Noise measurements on the floating diffusion input for charge-coupled devicesJournal of Applied Physics, 1974
- Transversal filtering using charge-transfer devicesIEEE Journal of Solid-State Circuits, 1973