Control and analysis of leakage currents in poly-Si thin-film transistors

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Abstract
Control of leakage current in autoregistered columnar and a solid phase crystallized poly‐Si thin‐film transistors (TFTs) is discussed. For n‐channel TFTs, two parasitic leakage current paths, due to bulk conduction and back interface conduction, have been identified. It is demonstrated that these can be controlled by using sufficiently thin films and by low dose boron back channel implants, respectively. By these means, generation limited leakage currents, with values of −14 A/μm of channel width, have been obtained. The minimum leakage currents, for n‐ and p‐channel TFTs, display the well‐known field enhancement which we confirm can be described by phonon assisted tunneling. In well‐engineered TFTs, with subthreshold slopes of <1 V/dec, we show that the drain fields required to promote the tunneling process are independent of the trap state density and result entirely from two‐dimensional gate‐drain coupling effects. Therefore, improving the quality of the poly‐Si will not reduce the exponential dependence of the leakage current on gate and drain bias, although the absolute value of leakage current will be reduced.