Interface properties of SiO2/n-GaN metal–insulator–semiconductor structures

Electrical characterization of ${\mathrm{SiO}}_2\mathrm{/n-}\mathrm{GaN}$ metal–insulator–semiconductor structures fabricated on sapphire substrates was performed by using high-frequency pulsed capacitance–voltage and capacitance-transient techniques. Fast and slow capacitance transients are clearly seen after applying reverse voltages, reflecting thermal emissions of carriers from the ${\mathrm{SiO}}_2/\mathrm{GaN}$ interface. The temperature dependence of the capacitance–voltage characteristics shows capacitance saturation in deep depletion (>15 V), which is probably associated with the slow capacitance transient. Deep-level transient spectroscopic measurements reveal two interface traps with activation energies of 0.71 and ∼0.76 eV from the conduction band, corresponding to the fast and slow capacitance transients, respectively. Therefore, the observed capacitance saturation may be due to Fermi-level pinning induced by the latter interface trap.