Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 37 (11) , 1398-1410
- https://doi.org/10.1109/12.8705
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- A Fault-Tolerant Modular Architecture for Binary TreesIEEE Transactions on Computers, 1986
- A Hypergraph Model for Fault-Tolerant VLSI Processor ArraysIEEE Transactions on Computers, 1985
- Wafer-Scale Integration of Systolic ArraysIEEE Transactions on Computers, 1985
- Configuration of VLSI Arrays in the Presence of DefectsJournal of the ACM, 1984
- On Area and Yield Considerations for Fault-Tolerant VLSI Processor ArraysIEEE Transactions on Computers, 1984
- The Diogenes Approach to Testable Fault-Tolerant Arrays of ProcessorsIEEE Transactions on Computers, 1983
- Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI DesignsIEEE Transactions on Computers, 1982
- Fault-tolerant wafer-scale architectures for VLSIACM SIGARCH Computer Architecture News, 1982
- Why systolic architectures?Computer, 1982
- Wafer-scale integration-a fault-tolerant procedureIEEE Journal of Solid-State Circuits, 1978