A new analog/digital CAD model for sub-halfmicron MOSFETs

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Abstract
In order for a model to be suitable for analog circuit simulation, a good accuracy and continuity in current and its derivatives in all operation regimes are required. As demonstrated in this paper. Our new model called MASTAR (Model for Analog and digital Simulation of mos TrAnsistoRs) perfectly satisfies these requirements. The gain in circuit CAD accuracy when using MASTAR as opposed to a conventional digital model is also demonstrated by comparison with data measured on test circuits. The validity of MASTAR has been confirmed on 4 generations of CMOS technologies : CMOS 1 /spl mu/m, 0.7 /spl mu/m. 0.5 /spl mu/m and recently also 0.35 /spl mu/m, with 20 nm, 15 nm, 12 nm and 8 nm gate oxides, respectively. It is worth noting that the first two are single-gate processes and the last two dual-gate ones. MASTAR works with 19 parameters per transistor. The total number of parameters for a given technology (geometrical dependencies included) is: 33 for a surface-channel and 32 for a buried-channel process. Among them there are 31 (30 for buried channel) physically based parameters and only 2 fitting ones.<>

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