An integrated modular and standard cell IC design method

Publisher Website

1 January 1984

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/isscc.1984.1156630

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

Algorithm for VLSI chip floor plan
Electronics Letters, 1983
Hierarchical Top-Down Layout Design Method for VLSI Chip
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982